1. Technical Field
The present invention relates to data processing systems and, more specifically, to disabling a system clock in such a system.
2. Description of the Related Art
Referring to FIG. 1, a block diagram representing a prior art system clock disabling signal processing circuit is shown. The system clock disabling signal may be generated due to the detection of an error or due to the occurrence of an event trigger. The processing path 50 consists of several groups or blocks of functional logic which includes staging latches 60, a cycle counter 70, an early-up chain 80 and clock control 90.
An event trigger is a signal representing a change of logic state at a particular data location which is responsible for triggering a specific response, such as the issuance of a system clock disable signal. Event triggers are often used in debugging operations. In this context, the occurrence of the event trigger at a predefined data location causes a clocks-off signal to be generated, arresting data propagation, so that interrogation of the machine state after the occurrence of the error may be had.
In normal data processing operations and in prior art debugging operations, a system clock disabling signal, whether coming from an event trigger or a generated error signal, or the like, must necessarily pass through the logic of FIG. 1 which performs the following functions.
The staging latches 60 are generally known in the art and provide the ability to induce a desired delay. For example, if the system clock cycles time is 10 ns and it is desired to have a delay of 100 ns, then 10 latches will be provided in the staging latches 60.
The cycle counter 70 is a mechanism which provides the ability to program which occurrence of an error or event trigger will cause the system clock to be disabled. For example, when a large scale data processing system is initially turned on, it will take some finite amount of time for data processing operations to reach a desired data flow rate. If it is determined, in such an instance, that the arrangement of data in the system for the first ten occurrences of a particular event trigger are not particularly interesting, the cycle counter may be set to count up (or down) ten times and on the eleventh time attain the count which generates a clocks-off signal. In this arrangement, the cycles counter 70 functions as an event trigger screening device.
The early-up chain 80 is essentially a device that transforms a signal with normal timing to a signal with early timing. The transformation takes a fixed number of clock cycles and it is independent of the clock cycle time. The transformation is provided because various units, operating in a data processing system, run on different clock phases to maximize processing speed and it is necessary to transform certain phases so that the system clock stops at an appropriate moment. Clock signals are referred to as early, normal and late, where early clocks have a minus phase shift with respect to the normal clock and late clocks have a plus phase shift with respect to the normal clock.
The clock control block 90 represents that logic which controls clock signals to the machine and which, in response to a clocks-off signal, turns off the system clock. Circuitry for performing the functions of the clock control block 90 is generally known in the art.
In prior art debugging techniques, an event trigger is often used to disable the system clock, whereupon the system is interrogated, eg., by scan-out or probing, or the like, to determine the system state. The use of the above-described functional logic 60, 70, 80, however, in a debugging scenario, induces a significant and disadvantageous delay from the time an error signal occurs to the time the clocks are actually turned off. This delay is approximately 16 cycles in one prior art machine which means that data is propagated for 16 clock cycles after an event occurs and before the disabling of the system clock. It is very difficult to analyze the flow of data for these 16 clock cycles to determine the actual state of the machine at the occurrence the event trigger.